Daniel Enériz

The development of real-time, reliable, low-cost automatic Phonocardiogram (PCG) analysis systems is critical for early detection of Cardiovascular Diseases (CVDs), especially in countries with limited access to primary health care programs. Once the raw PCG acquired by the stethoscope has been preprocessed, the first key task is its segmentation into the fundamental heart sounds. For this purpose, an optimized hardware implementation of the segmentation algorithm is essential to attain a computer-aided diagnostic system based on PCGs. This paper presents the optimization of a U-Net-based segmentation algorithm for its implementation in a low-end Field-Programmable Gate Array (FPGA) using low-resolution fixed-point data types. The optimization strategies seek to reduce the system latency while maintaining a constrained consumption of FPGA resources, aiming for a real-time response from the stethoscope data acquisition to the CVDs detection. Experimental results prove a 64% decrease in latency compared to a baseline version, a 3.9% reduction of Block Random Access Memory, which is the limiting resource of the design, and a 70% reduction in energy consumption. To the best of our knowledge, this is the first work to exhaustively study different optimization strategies for implementing a large 1D U-Net-based model, achieving real-time fully characterized performance.

The use of Convolutional Neural Networks (CNNs) to process Electroencephalograph (EEG) signals has been introduced in recent years with great success in the field of Brain-Computer Interfaces (BCI). Nevertheless, in order to advance towards a CNN-based BCI prototype, they must be efficiently mapped into low-power and low-cost hardware, enabling a real-time, portable and Internet-independent brain-computer communication. This work presents the implementation of an EEGNet-based model into an ARM Cortex M4F microcontroller, available on the Arduino Nano 33 Sense. Starting from models trained over the Physionet Motor Movement/Imagery dataset, 8-bit integer post-training quantization has been considered to reduce computing complexity, with a mean downgrade of 2.64±0.77% in accuracy. Moreover, their computational impact and memory footprint have been characterized by measuring the associated operations and Random-Access Memory (RAM) usage. Finally, a selected model has been implemented on the ARM Cortex M4F, with a latency of 137 ms and an energy per inference of 2.55 mJ, a 40% lower than other EEGNet implementation on the same microcontroller.

Multichannel electroencephalograph (EEG) signals data acquisition is non-invasive and easy to implement, thus being the preferred brain-related information carriers for Brain Computer Interfaces (BCIs). Since BCIs must be capable of processing information in real-time, their implementation in edge devices is currently being boosted, particularly on Field-Programmable Gate Arrays (FPGA). In this work, a real-time EEG acquisition system based on the XADC of the Xilinx Zynq FPGA is presented, meeting the requirements of a well-known BCI processing algorithm, the EEGNet. Performed tests show minimal error in the acquisition, whose effects in the EEGNet accuracy are negligible.

One of the most popular Brain-Computer Interface (BCI) paradigms is the classification of motor imagery tasks using Electroencephalograph signals (EEG). Recent works suggest the use of Convolutional Neural Networks (CNNs) to both extract the EEG features and classify them in a single compact solution. Since BCIs are meant to be run in embedded hardware, compact models and data reduction strategies are necessary. An EEGNet-based model is presented in this work, which achieves results similar to those of the state-of-the-art of 83.15 %, 75.74 % and 65.75 % in classification accuracy on 2-, 3-, and 4-class MI tasks in global validation on the Physionet Motor Movement/Imagery dataset. Taking advantage of its lower model complexity, a preliminary FPGA processor design using fixed-point datatypes is introduced, to evaluate resources consumption and latency on a low-spec system on chip approach.

The continuous development of more accurate and selective bio- and chemo-sensors has led to a growing use of sensor arrays in different fields, such as health monitoring, cell culture analysis, bio-signals processing, or food quality tracking. The analysis and information extraction from the amount of data provided by these sensor arrays is possible based on Machine Learning techniques applied to sensor fusion. However, most of these computing solutions are implemented on costly and bulky computers, limiting its use in in-situ scenarios outside complex laboratory facilities. This work presents the application of machine learning techniques in food quality assessment using a single Field Programmable Gate Array (FPGA) chip. The characteristics of low-cost, low power consumption as well as low-size allow the application of the proposed solution even in space constrained places, as in food manufacturing chains. As an example, the proposed system is tested on an e-nose developed for beef classification and microbial population prediction.

Nowadays, most of the automatized measurement processes are carried out by VISA (Virtual Instrument Software Architecture) compatible instruments, that execute the instructions provided by a host computer connected through wired standard buses, as USB (Universal Serial Bus), GPIB (General-Purpose Instrumentation Bus), PXI (PCI eXtensions for Instrumentation) or Ethernet. To overcome the intrinsic limitations associated to these wired systems, this work presents an instrumentation control system based on the IEEE 802.11 wireless communications standard. Intended for instruments having a USB control port, this port is connected to a gateway based on a compact Raspberry Single Board Computer (SBC) and thus the instrument can be connected to the host computer via Wireless Fidelity (WiFi), easily allowing the deployment of an ad-hoc instruments communication network in the working area or its connection to a previously deployed general purpose WiFi network. Developed under Python, the operation commands, wireless link protocol, and USB connection allow two modes of operation to provide system flexibility: a live mode, where commands are sent individually from the host computer to the selected instrument; and a standalone mode, where a full measurement process can be entirely downloaded in the gateway to be autonomously executed on the instrumentation. The system performance in both operation modes, distance of operation, time latencies, and operating lifetime in battery operation have been characterized.